Embodiments of the application described herein relate to a memory system, and more particularly, relate to a memory system and a system on chip including a linear remapper and an access window.
A memory system may include two or more processors. For example, a mobile system may include a modem and an application processor (AP) (or, multimedia processor). A memory system that includes two or more processors may necessitate at least two or more memories for driving the processors, respectively.
In the above example, the modem may accompany a NOR flash memory for storing codes and a DRAM for executing the codes. The application processor may accompany a NAND flash memory for storing codes and data and a DRAM for executing the codes. Codes and data may be exchanged between the modem and the application processor through an interface, such as UART (Universal Asynchronous Receiver Transmitter), SPI (Serial Peripheral Interface), or SRAM interface.
The memory system may perform an interleaving access operation using two or more DRAMs. That is, the memory system accesses two or more memories in turn to improve its performance. The interleaving access system may have the following problem. In the event that performance is not problematic even though one DRAM in an interleaving access system is only accessed, power is unnecessarily consumed because two DRAMs are used.